Programmable devices, such as SRAM-based FPGAs, can be rapidly reconfigured to perform many different functions. Typically, programmable devices include a number of different functional units connected by programmable interconnections. The functions of programmable device are determined by configuration data. Configuration data is loaded into the programmable device and defines the configuration of the functional units and the programmable interconnections. This, in turn, defines the overall functions of the programmable device.
To test programmable devices, test configuration data is loaded into a programmable device to define one or more test functions. The test functions are then tested to ensure that the programmable device is operating properly. Typically, testing a programmable device requires reconfiguration with thousands of different sets of test configuration data to achieve sufficient test coverage. It is desirable to reduce the time, and consequently the cost, of testing for programmable devices.
Loading test configuration data is one of the most time-consuming portions of the test process. Typically, test configuration data must be transferred from a test apparatus into the internal configuration memory of a programmable device. Configuration memory is typically divided into a number of configuration words. Each configuration word defines the configuration of a portion of the programmable device. Typically, a configuration word has far more bits than the number of input pins available for loading configuration data. For example, configuration words may have hundreds or thousands of configuration bits. One prior system for setting the value of each configuration word is to divide each configuration word into a number of configuration blocks. Each configuration block is treated as a large shift register and is assigned to a different input pin. In this system, configuration data is serially loaded into each configuration block. This system can take thousands of clock cycles to load configuration data for a single test, making testing time-consuming and expensive.
Another prior system for loading test configuration data divides the configuration word into a number of configuration blocks. This system loads configuration data into a configuration block in parallel. Each configuration block is simultaneously loaded with identical configuration data. If each configuration block has the same number of bits as there are input pins, then configuration data for an entire configuration word can be loaded in a single clock cycle.
This system's “all or nothing” approach to repeatability leads to problems. If different configuration data needs to be loaded into different blocks, this system cannot be used. This can often occur when configuration data is not symmetrical on a block-wise basis, or when the programmable device architecture is asymmetrical. In these situations, another system for loading configuration data, such as the serial loading system discussed above must be used. Thus, when configuration data violates block-wise symmetry in even a minor way, the system punishes this digression with a maximum load cost. This is especially inefficient because typical configuration data includes a large number of 0's interspersed between a few 1's.
It is desirable to improve the efficiency of loading configuration data into programmable devices with asymmetrical configuration data. It is further desirable to allow for loading of configuration data using one of several alternate systems to maximize the efficiency of the loading process.